The present invention is generally directed to a di-phase pulse receiving system of the type which receives a plurality of transmitted serial di-phase data bits and more particularly to a control means for such a receiving system for converting the serial di-phase data bits into parallel data bits having corresponding discrete logic levels.
Di-phase pulse transmission is well known in the art. In such transmission, a series of alternate positive and negative pulses are transmitted in pairs wherein the relative order of the positive and negative pulses of each pair defines a discrete logic level. For example, and as used in practicing the present invention, a pulse pair having a negative pulse preceding a positive pulse corresponds to a logical one bit and a pulse pair consisting of a positive pulse preceding a negative pulse corresponds to a logical 0 bit. Di-phase pulse transmission has found wide acceptance because there are as many positive pulses transmitted as negative pulses which thereby eliminates DC components.
In order to take full advantage of the di-phase pulse transmission technique, di-phase pulse receiving systems have been devised wherein the serial di-phase data bits are converted to corresponding discrete logic levels representing bits of information and made available to subsequent circuitry in parallel to afford action by the subsequent circuitry on the data bits.
Receiving di-phase data bits and converting them to parallel bits of corresponding discrete logic levels becomes difficult as the repetition rate of the di-phase pulse transmission increases. For example, at di-phase transmission rates on the order of 5 Megahertz, the reception and conversion of the di-phase pulses becomes extremely difficult. Di-phase pulse receiving systems of the prior art have experienced such difficulty. One reason for this is that the prior art di-phase pulse receiving systems have generally been complicated and thus overly cumbersome when receiving di-phase pulse transmissions at such a high rate.
It is, therefore, a general object of the present invention to provide a new and improved di-phase pulse receiving system which is capable of receiving di-phase pulse transmissions which are transmitted at high rates.
It is a particular object of the present invention to provide a new and improved control means for a di-phase pulse receiving system which renders the receiving system capable of receiving di-phase pulse transmissions at rates of 5 Megahertz and converts the serial di-phase data bits into parallel bits baving corresponding discrete logic levels.
It is a still further particular object of the present invention to provide a control means for a di-phase pulse receiving system which is relatively simple in design and which resets itself after receipt of each serial data bit of a di-phase pulse transmission.